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[7์ฃผ์ฐจ] Virtual Memory Management: Cost model, HW components

by ํฌ์ŠคํŠธ์‰์ดํฌ 2023. 1. 15.

Virtual Memory Management: Cost model, HW components

Virtual Memory Management

โœ” ๊ฐ€์ƒ ๋ฉ”๋ชจ๋ฆฌ(๊ธฐ์–ต ์žฅ์น˜)

โœ” ๊ฐ€์ƒ ๋ฉ”๋ชจ๋ฆฌ ๊ด€๋ฆฌ์˜ ๋ชฉ์ 

  • ๊ฐ€์ƒ ๋ฉ”๋ชจ๋ฆฌ์˜ ์‹œ์Šคํ…œ ์„ฑ๋Šฅ ์ตœ์ ํ™”
    • Cost Model
    • ๋‹ค์–‘ํ•œ ์ตœ์ ํ™” ๊ธฐ๋ฒ•

Cost Model for VM System

โœ” Page fault frequency (๋ฐœ์ƒ ๋นˆ๋„)
โœ” Page fault rate (๋ฐœ์ƒ๋ฅ )

โœ” Page fault rate๋ฅผ ์ตœ์†Œํ™” ํ•  ์ˆ˜ ์žˆ๋„๋ก ์ „๋žต๋“ค์„ ์„ค๊ณ„ํ•ด์•ผ ํ•œ๋‹ค

  • context switch ๋ฐ kernel ๊ฐœ์ž…์„ ์ตœ์†Œํ™”
  • ์‹œ์Šคํ…œ ์„ฑ๋Šฅ ํ–ฅ์ƒ

โœ” Page reference string(d)

  • ํ”„๋กœ์„ธ์Šค์˜ ์ˆ˜ํ–‰ ์ค‘ ์ฐธ์กฐํ•œ ํŽ˜์ด์ง€ ๋ฒˆํ˜ธ ์ˆœ์„œ

โœ” Page fault rate = F(w)

  • ํŽ˜์ด์ง€ ํดํŠธ ์ˆ˜ / ํŽ˜์ด์ง€ ์ „์ฒด์˜ ๊ธธ์ด

Hardware Components

โœ” Address translation device(์ฃผ์†Œ ์‚ฌ์ƒ ์žฅ์น˜)

  • ์ฃผ์†Œ ์‚ฌ์ƒ์„ ํšจ์œจ์ ์œผ๋กœ ์ˆ˜ํ–‰ํ•˜๊ธฐ ์œ„ํ•ด ์‚ฌ์šฉ
  • ex) TLB, Dedicated page-table register, Cache memories

โœ” Bit vectors

  • Page ์‚ฌ์šฉ ์ƒํ™ฉ์— ๋Œ€ํ•œ ์ •๋ณด๋ฅผ ๊ธฐ๋กํ•˜๋Š” ๋น„ํŠธ
  • Reference bits (used bit)
    • ์ฐธ์กฐ ๋น„ํŠธ
  • Update bits (modified bits, write bits, dirty bits)
    • ๊ฐฑ์‹  ๋น„ํŠธ

Bit vectors

Reference bit vector

โœ” ๋ฉ”๋ชจ๋ฆฌ์— ์ ์žฌ๋œ ๊ฐ๊ฐ์˜ page๊ฐ€ ์ตœ๊ทผ์— ์ฐธ์กฐ ๋˜์—ˆ๋Š”์ง€๋ฅผ ํ‘œ์‹œ

โœ” ์šด์˜

  1. ํ”„๋กœ์„ธ์Šค์— ์˜ํ•ด ์ฐธ์กฐ๋˜๋ฉด ํ•ด๋‹น page์˜ referece bit๋ฅผ 1๋กœ ์„ค์ •
  2. ์ฃผ๊ธฐ์ ์œผ๋กœ ๋ชจ๋“  reference bit๋ฅผ 0์œผ๋กœ ์ดˆ๊ธฐํ™”

โœ” Reference bit๋ฅผ ํ™•์ธํ•จ์œผ๋กœ์จ ์ตœ๊ทผ์— ์ฐธ์กฐ๋œ page๋“ค์„ ํ™•์ธ ๊ฐ€๋Šฅ

Update bit vector

โœ” Page๊ฐ€ ๋ฉ”๋ชจ๋ฆฌ์— ์ ์žฌ ๋œ ํ›„, ํ”„๋กœ์„ธ์Šค์— ์˜ํ•ด ์ˆ˜์ • ๋˜์—ˆ๋Š”์ง€๋ฅผ ํ‘œ์‹œ

โœ” ์ฃผ๊ธฐ์  ์ดˆ๊ธฐํ™” ์—†์Œ

  • ํ•ด๋‹น page๊ฐ€ ๋ฉ”๋ชจ๋ฆฌ์—์„œ ๋‚˜์˜ฌ ๋•Œ ์ดˆ๊ธฐํ™”

โœ” Update bit = 1

  • ํ•ด๋‹น page์˜ (Main memory ์ƒ ๋‚ด์šฉ) != (Swap device ๋‚ด์šฉ)
  • ํ•ด๋‹น page์— ๋Œ€ํ•œ write-back(to swap device)์ด ํ•„์š”

๋Œ“๊ธ€